Course on STA and Timing Constraints
Learn each and everything about STA and timing constraints
Lectures -26
Duration -2.5 hours
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Course Description
This course all basic concepts in Static Timing Analysis and Timing Constraints
- Introduction to Static Timing Analysis
- Timing Paths
- Startpoint, Endpoint, Combinational Logic
- Setup and Hold Check Definition
- Understanding details of setup slack calculation
- Multiple types of Timing Paths
- Design Rule Checks
- Timing checks on Async Pins
- Clock Gating Checks
- Timing Latches
- STA in presence of Multiple Clocks
- Timing Arcs
- Cell Delays and Models
- Impact of clock network on STA
- Understanding Text Report in STA
- Overview of SDC
- Clock and Generated Clock Definitions
- Clock Groups
- Clock Characteristics Specification
- Port Delays
- Timing Exceptions
- Other SDC commands
Goals
Learn all the basics of STA and timing constraints
Prerequisites
Basics of logic and digital design
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Curriculum
Check out the detailed breakdown of what’s inside the course
Introduction
1 Lectures
-
Introduction 00:30 00:30
STA Definition
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Timing paths
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Timing path elements
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Setup and hold checks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Slack calculation
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Other timing checks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Design rule checks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Checks on async pins
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Clock gating checks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Latch timing
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Multiple clocks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Timing arc and timing sense
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Cell delays and clock network
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Setup and hold detailed
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
STA text report
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Crosstalk and noise
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Operating modes and other variations
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
SDC overview
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Clocks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Generated clocks
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Clock groups
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Clock properties
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Boundary constraints
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Timing exceptions
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Multiple modes
1 Lectures
![Tutorialspoint](/market/public/assets/images/loader.gif)
Instructor Details
![Vikas Sachdeva](https://www.tutorialspoint.com/assets/profiles/717236/profile/200_3500486-1698324283.jpg)
Vikas Sachdeva
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