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Memory Write (MW) machine cycle in 8085 Microprocessor
In the last three clock cycles the instructions ‘MVI M, 25H’ are the example for Memory Write machine cycle. We have shown the Waveforms for MW machine cycle are shown in fig below.
The address which is sent out from the register pair in a Memory Write machine cycle is completely dependent on the MW machine cycle under the consideration as it is shown in the chart below.
| Reg. pair | Example |
|---|---|
| SP | We push the information above the top of the stack in PUSH B |
| HL | We save register C in the memory which is pointed by HL in MOV M, C |
| BC | We save register A register in the memory which is pointed by BC in STAX B |
| DE | We save register A register in the memory which is pointed by DE in STAX D |
| WZ | We save register A in the location 1234H in STA 1234H |
Here is the detailing of the instruction execution –
In 8085 Instruction set, this instruction MVI M, d8 is used to load a memory location pointed by HL pair with an 8-bit value directly. This instruction uses immediate addressing for specifying the data. It occupies 2-Bytes in memory.
| Mnemonics, Operand | Opcode (in HEX) | Bytes |
|---|---|---|
| MVI M, Data | 36 | 2 |
As an example, we can consider MVI M, ABH as an example instruction of this type. It is a 2-Byte instruction, with opcode for MVI M using up one Byte, and ABH using up another more Byte. We are considering that HL register pair is containing 16-bit address 4050H and content of that address initially CDH. So after execution of the instruction the updated values will be -
| | Before | After |
|---|---|---|
| (HL) | (4050) | (4050) |
| (4050) | CDH | ABH |
Table is Shown Below
| Address | Hex Codes | Mnemonic | Comment |
|---|---|---|---|
| 2006 | 36 | MOV M, ABH | Content of the memory location pointer by HL register pair will get updated by ABH |
| 2007 | AB | | Operand ABH |
Let us check the timing diagram of this instruction MVI M, ABH
Summary: So this instruction MVI M, ABH requires 2-Bytes, 3-Machine Cycles (Opcode Fetch, Memory Read, Memory Write) and 10 T-States for execution as shown in the timing diagram.
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