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Instruction type DCX rp in 8085 Microprocessor
In 8085 Instruction set, DCX is a mnemonic that stands for “DeCrementeXtended register” and rp stands for register pair. And it can be any one of the following register pairs −
rp = BC, DE, or HL
This instruction will be used to subtract 1 from the present content of the rp. And thus the result of the decremented content will remain stored in rp itself. Though, it is an arithmetic instruction, note that flags are not at all affected by the execution of this instruction. A register pair is generally used to store 16-bit memory address. If flag bits got affected during decrement of a memory address, then it may cause problems in many cases. So as per design of 8085, flag bits are not getting affected by the execution of this instruction DCXrp.
As rp can have any one of the three values, there are three opcodes for this type of instruction. It occupies only 1-Byte in memory.
| Mnemonics, Operand | Opcode(in HEX) | Bytes |
|---|---|---|
| DCX B | 0B | 1 |
| DCX D | 1B | 1 |
| DCX H | 2B | 1 |
Let us consider DCX B as a sample instruction falling in this category. As it is a 1-Byte instruction, so it will occupy single 1-Byte location in the memory. Let us consider that the initial content of register pair BC is 4055H. So after execution of the instruction DCX B, the new content of BC register pair would be 4054H. The result of execution of this instruction is shown below with the help of a tracing table −
| Before | After | |
|---|---|---|
(BC) |
4055H | 4054H |
| Address | Hex Codes | Mnemonic | Comment |
|---|---|---|---|
| 2003 | 0B | DCX B | BC = BC – 1 |
We may think that DCX B is similar to DCR C in this example. But that is not true. As if the initial content of BC register pair be 2000H then after DCR C instruction execution it would be 20FFH not 1FFFH.So, basically, DCX instruction decrements a 16-bit quantity, whereas DCR decrements an 8-bit quantity.
Here is the timing diagram of the instruction execution DCX B as below −
Summary − So this instruction DCX B requires 1-Byte, 1-Machine Cycle (Opcode Fetch) and 6 T-States for execution as shown in the timing diagram.
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