Pipelining is a very effective method for speeding up instruction execution along a sequential path. But if a branch introduces the pipeline and disorganizes the sequential processing, the implementation of the pipeline will be seriously disrupted unless appropriate methods are used.It can indicate the problems that generate branches in pipelines. ... Read More

Conditional branch instructions are used mainly in two situations. Most frequently they are employed to check the result of instruction for a specified condition, such as whether the result equals 0, if it is negative, and so on.If the specified condition is met, control is transferred to a given location ... Read More

A branch in a computer program is an instruction that communicates a device to start implementing several instructions instead of simply performing the instructions in order. In high-level languages, these are defined as flow control phases and are established into the language. In assembly programming, branch instructions are established into ... Read More

The design space of instruction dispatch is complex. In some respects, it resembles that of instruction issue but it has two additional aspects, as shown in the figure.Dispatch Policy − The dispatch policy can be considered as a scheduling policy consisting of the components as −Selection Rule − The selection ... Read More

Shelving is an advanced issue mode, which is employed to eliminate issue blockages due to dependencies. Shelving makes use of dedicated instruction buffers, called shelving buffers, in front of each EU. The design space of shelving is shown in the figure. It consists of the following four main components such ... Read More

VLIW ArchitectureVLIW represents a Very long instruction word. It is an instruction set architecture constructed to take complete benefit of instruction-level parallelism (ILP) for upgraded performance.Central processing unit processors enable programs to designate instructions to execute in order only whereas a VLIW processor enables programs to explicitly determine instructions to ... Read More

The PentiumPro is the flagship of Intel’s x86 line of processors. The Pentium Pro processor performs a dynamic implementation microarchitecture such as a specific set of multiple branch prediction, data flow analysis, and speculative implementation. The Pentium Pro processor has a decoupled, 12- phases, super pipelined implementation, trading less work ... Read More

The PowerPC 620 is the highest performance model of the PowerPC line. It is the first chip for the application server and high-tech office product line inside the PowerPC family. It uses a high-execution microarchitecture with several advanced superscalar features to exploit instruction-level parallelism.The PowerPC 620 has six EUs capable ... Read More

The MIPS R10000 is the latest architecture of the R line of processors. It implements the MIPS IV ISA (Instruction Set Architecture), which is a superset of the MIPS III, supported for instance by the R8000. At a planned clock rate of 200 MHz, this four-way superscalar processor has a ... Read More

ROB stands for reorder buffer. The ROB was first expressed by Smith and Pleszkun in 1988. They conceived the ROB to solve the precise interrupt problem. The ROB is a round buffer with head and tail pointers.The head pointer denotes the area of the next complimentary entry. Instructions are written ... Read More