Snoopy cache protocols are very popular in shared bus multiprocessors due to their relative simplicity. They have both write-update and write-invalidate policy versions. Write-invalidate snoopy cache protocols resemble this protocol in many ways and therefore are also easy to understand after studying a write-update protocol.The definition of transmission routes of ... Read More

Hardware-based protocols support general solutions to the issues of cache coherence without any condition on the cachability of data. Hardware-based protocols can be classified as follows −Memory update policy − There are two types of memory update policy are used in multiprocessors. The write-through policy maintains consistency between the main ... Read More

In multistage network-based shared memory systems, thousands of processors can try for a similar memory location. This location is called a hotspot and can significantly enlarge latency in the interconnection network. When two processors attempt to access the same memory location, their message will conflict in one of the switches ... Read More

The limited bandwidth of the single shared bus represents a major limitation in building scalable multiprocessors. There are several ways to increase the bandwidth of the interconnection network. A natural idea is to multiply the number of buses, like the processors and memory units. Four different ways have been proposed ... Read More

Arbiter logic plays a crucial act in the implementation of pended and split-transaction buses. These are the so-called 1 of N arbiters since they grant the requested resource only to one of the requesters. The design space of arbiter logic is very rich. There are two ways to organize the ... Read More

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines ... Read More

COMA stands for Cache-only memory access machines. A COMA machine includes several processing nodes connected by an interconnection network. Each processing node has a high-implementation processor, a cache, and an allocation of the global shared memory.COMA machines try to avoid the problems of static memory allocation of NUMA and CC-NUMA ... Read More

CC-NUMA stands for Cache-coherent non-uniform memory access machines. A CC-NUMA machine includes several processing nodes linked through a high-bandwidth low-latency interconnection network. Each processing node includes a high-implementation processor, the related cache, and an allocation of the global shared memory.Cache coherence is preserved by a directory-based, write-invalidate cache coherence protocol. ... Read More

Cray T3D is the most recent NUMA machine that was designed to provide a highly scalable parallel supercomputer that can incorporate both the shared memory and the message-passing programming paradigms. As in other NUMA machines, the shared memory is distributed among the processing elements to avoid the memory access bottleneck ... Read More

Hector is a hierarchical NUMA machine consisting of stations connected by a hierarchy of ring networks. Stations are symmetric multiprocessors where the processing modules are linked by an individual bus. Nodes comprise three main units − a processor/cache unit, a memory unit, and the station bus interface which connects the ... Read More