Cube-connected networks are patterned after the n-cube structure. An n-cube (hypercube of order n) is defined as an undirected graph having 2n vertices labeled 0 to 2n - 1 such that there is an edge between a given pair of vertices if and only if the binary representation of their ... Read More

Static (fixed) interconnection networks are characterized by having fixed paths, unidirectional or bidirectional, between processors. Two types of static networks can be identified. These are completely connected networks (CCNs) and limited connection networks (LCNs).Completely Connected NetworksIn a completely connected network (CCN) each node is connected to all other nodes in ... Read More

Blocking NetworksBlocking networks possess the property that in the presence of a currently established interconnection between a pair of input/output, the arrival of a request for a new interconnection between two arbitrary unused input and output may or may not be possible. Examples of blocking networks include Omega, Banyan, Shuffle–Exchange, ... Read More

In this type of network, connections among processors and memory modules are made using simple switches. There are three basic interconnection topologies such as crossbar, single-stage, and multistage.Crossbar NetworksA crossbar network defines the other extreme to the limited single bus network. While the single bus can provide only a single ... Read More

MIMD stands for Multiple-instruction multiple-data streams. It includes parallel architectures are made of multiple processors and multiple memory modules linked via some interconnection network. They fall into two broad types including shared memory or message passing.A shared memory system generally accomplishes interprocessor coordination through a global memory shared by all ... Read More

SIMD represents single-instruction multiple-data streams. The SIMD model of parallel computing includes two parts such as a front-end computer of the usual von Neumann style, and a processor array as displayed in the figure.The processor array is a collection of identical synchronized processing elements adequate for simultaneously implementing the same ... Read More

The flow of vector operands between the main memory and vector registers is generally pipelined with various access paths. In this section, we specify vector operands and describe three vector-access schemes from interleaved memory modules allowing overlapped memory accesses.Vector Operand Specifications − Vector operands can have arbitrary lengths. Vector elements ... Read More

A vector is a set of scalar data elements, all of similar type, saved in memory. The vector elements are ordered to have a permanent addressing increment between successive elements known as the stride.A vector processor is an ensemble of hardware resources, such as vector registers, functional pipelines, processing elements, ... Read More

Parallel algorithms are those specially devised for parallel computers. The idealized parallel algorithms are those written for the PRAM models if no physical constraints or communication overheads are imposed. In the real world, an algorithm is considered efficient only if it can be cost-effectively implemented on physical machines. In this ... Read More

A distributed-memory multicomputer system is modeled in the figure. The system includes multiple computers known as nodes, related by a message-passing network. Each node is an independent computer including a processor, local memory, and sometimes connected disks or I/O peripherals.The message-passing network supports point-to-point static connections among the nodes. All ... Read More