There are two types of operands fetch policies such as issue bound or dispatch bound. The issue-bound fetch policy defines that operands are fetched during instruction issues. In this method, shelving buffers influence instructions with their operand values, needing that the buffers be fully long to support space for all the source operands.The other basic operand fetch policy is the dispatch bound fetch policy, when operands are fetched during dispatching. In this case, shelving buffers contain short register identifiers instead of long operands.The issue bound fetch policyIn this case, while issuing the instructions, the referenced source register numbers are forwarded ... Read More

Shelving buffers have three major aspects such as the type and capacity of the buffers used and the number of their read and write ports, as shown in the figure.Types of shelving buffersThere are two generic types of shelving buffers such as standalone shelving buffers and combined buffers which are used for shelving, renaming, and reordering as shown in the figure.In most cases shelving buffers are implemented as standalone shelving buffers, that is, buffers that are utilized particularly for shelving. This type of shelving buffer is usually designated reservation stations. In the superscalar processor, reservation stations are executed using three ... Read More

A superscalar processor is created to produce an execution rate of more than one instruction per clock cycle for a single sequential program. Superscalar processor design generally defines a set of techniques that enable the central processing unit (CPU) of a computer to obtain a throughput of more than one instruction per cycle while implementing a single sequential program.The concept of the superscalar issue was first developed as early as 1970 (Tjaden and Flynn, 1970). It was later reformulated more precisely in the 1980s (Torng, 1982, Acosta et al, 1986).The function of superscalar processing is the superscalar instruction issue. A ... Read More

The following methods used in instruction issue policies such as the scalar processors, superscalar processors, and the broad picture covering both. While considering the most frequently used issue policies, it can reduce the design space of instruction issues by ignoring less important aspects.First, for both scalar and superscalar processors, it can avoid issue order, because most processors employ an in-order issue. Moreover, it can discard issue alignment in the case of scalar and superscalar processors that make use of shelving.While considering instruction issue policies for scalar processors, it should be treated the three basic issue aspects such as whether to ... Read More

The handling of issue blockages can be broken into two types as displayed in the figure. The first aspect called preserving issue order specifies whether a dependent instruction blocks the issue of subsequent independent instructions in the issue window. The second aspect is the alignment of instruction issue. It decides whether a fixed or gliding issue window is used.As shown in the figure, if a dependent instruction such as instruction b, blocks the issues of all subsequent instructions until the dependency is resolved, the issue order is known as ‘in-order’.However, restricting subsequent independent instructions from the issue can extremely disrupt ... Read More

Superscalar instruction issue is the most sensitive task of superscalar operation. The issue policy determines how dependencies are managed during the issue process. The issue rate defines the maximum number of instructions a superscalar processor can issue in each cycle.The design space of issue policy is complex. As shown in the figure, it consists of four major aspects. The first two define how false data and unresolved control dependencies are coped with during instruction issues. In both cases, the design options are to prevent them during instruction issues by using register renaming and speculative branch processing.The third condition decides whether ... Read More

A scalar processor has to decode only a single instruction in each cycle as shown in the figure. In addition, a pipelined processor has to check for dependencies to decide whether this instruction can be issued or not. In comparison, a superscalar processor has to perform a much more complex task.As shown in the figure, it has to decode multiple instructions, say four, in a single clock cycle. It also needs to check for dependencies from two perspectives: First, whether the instructions to be issued are dependent on the instructions currently in execution. Second, whether there are dependencies among the ... Read More

Superscalar processing can be broken down into several particular tasks, which is shown in the figure. Superscalar processors can issue multiple instructions per cycle, the first task certainly is parallel decoding.Decoding in superscalar processors is a significantly more complex task than in the case of scalar processors and evolves into even more sophisticated as the issue rate improves.Higher issue rates can immensely extend the decoding cycle or can provide growth to various decoding cycles unless decoding is increased. An increasing technique of improvement is pre-decoding.This is partial decoding implemented in advance of typical decoding, while instructions are loaded into the ... Read More

A superscalar processor is created to produce an implementation rate of more than one instruction per clock cycle for a single sequential program. Superscalar processor design defines as a set of methods that enable the central processing unit (CPU) of a computer to manage the throughput of more than one instruction per cycle while performing a single sequential program.While there is not a global agreement on the interpretation, superscalar design techniques involve parallel instruction decoding, parallel register renaming, speculative execution, and out-of-order execution. These techniques are usually employed along with complementing design techniques including pipelining, caching, branch prediction, and multi-core ... Read More

The concrete architecture at a given level is normally defined in the phrase of its components. Hence, the description of the concrete architecture at a given level is based on the abstract architectures of its components.As an effect, the concrete architecture at a specific level is a description at a higher abstraction level than the corresponding abstract architecture at the subsequent lower level.Thus, we can define that the sequence of theory of concrete and abstract architectures at successive levels yields a description framework at following higher levels of abstraction.Therefore, the three-level architecture description design considered, with independent concrete and abstract ... Read More