There are two possible ways of extending the basic concepts such as increasing the multiplicity of delay slots or introduce annulment of instruction in the delay slot. Most architecture provides one delay slot only. Few architectures are offering multiple delay slots, such as the MIPS-X.The other possibility to fill more delay slots is to introduce annulment (also called nullification or squashing). The basic idea is to introduce options in using delay slots, which can permit more delay slots to be filled than in the case of the basic scheme. Four different types of annulment can be introduced. The four variants ... Read More

When branches are processed by a pipeline simply, after each taken branch, at least one cycle remains unutilized. This is because of the assembly line-like apathy of pipelining. Instruction slots following branches are known as branch delay slots.Delay slots can also appear following load instructions; these are defined load delay slots. Branch delay slots are wasted during traditional execution. However, when delayed branching is employed, these slots can be at least partly used.Principle of Delayed branchingtiti+1ti+2ti+3ti+4BbFDEWBAaddFDEWBCsubFDBTAFIn the figure, it can transfer the add instruction of our program segment that initially preceded the branch into the branch delay slot. With delayed ... Read More

Processors use a large variety of approaches and techniques for branch handling. Three methods give an increase to the basic methods of in-branch handling. These are as follows −whether branch delay slots are usedhow unresolved conditional branches are handledwhether the architecture provides represents to prevent conditional branches.The fundamental approaches to branch handling reflect these questions. According to how to branch handling responds to these questions it can determine delayed branching, blocking and speculative branch processing, multiway branching, and guarded execution.The first method is whether branch delay slots are used. The simple branch handling generally results in one or two wasted ... Read More

It can evaluate and compare different branch processing techniques, it can require a performance measure. Let us consider the execution of a branch instruction in a four-stage pipeline as shown in the figure. If the branch is processed straightforwardly, the branch target address (BTA) will be computed in cycle ti+3.Then the branch target instruction can be fetched in cycle ti+4. Thus, the branch target instruction is fetched with a 3 cycles delay in comparison to the fetching of the branch instruction. This means a 2-cycle penalty compared to the sequential processing.The performance of branch processing in a certain typical situation. ... Read More

Pipelining is a very effective method for speeding up instruction execution along a sequential path. But if a branch introduces the pipeline and disorganizes the sequential processing, the implementation of the pipeline will be seriously disrupted unless appropriate methods are used.It can indicate the problems that generate branches in pipelines. Let us suppose the implementation of an unconditional branch in a pipeline. An unconditional branch is implemented on a traditional RISC pipeline when no specific care is taken to boost adaptability.The pipeline is considered to process instructions in four subsequent cycles, such as, in the consecutive fetch (F), decode (D), ... Read More

Conditional branch instructions are used mainly in two situations. Most frequently they are employed to check the result of instruction for a specified condition, such as whether the result equals 0, if it is negative, and so on.If the specified condition is met, control is transferred to a given location in the program. The other usual situation is to compare two operands, asking whether they are equal, for instance, and then to approach a given location if the specified condition is met.There are two basic approaches to how instruction set architectures (ISA) check the results of operations such as the ... Read More

A branch in a computer program is an instruction that communicates a device to start implementing several instructions instead of simply performing the instructions in order. In high-level languages, these are defined as flow control phases and are established into the language. In assembly programming, branch instructions are established into a CPU.Branches are used to transmission control, unconditionally or conditionally, to a stated position of the program. Unconditional branches are continually taken. In contrast, conditional branches contain a condition and thus are either taken or not taken, based on either the particular condition is true or false.As shown in the ... Read More

The design space of instruction dispatch is complex. In some respects, it resembles that of instruction issue but it has two additional aspects, as shown in the figure.Dispatch Policy − The dispatch policy can be considered as a scheduling policy consisting of the components as −Selection Rule − The selection rule specifies when instructions are studied executable. Let us take it for granted that renaming is employed and unresolved conditional transfer instructions are managed by speculative branch processing.Arbitration Rule − It can also need an arbitration rule for the case when more instructions are eligible for execution that can be ... Read More

Shelving is an advanced issue mode, which is employed to eliminate issue blockages due to dependencies. Shelving makes use of dedicated instruction buffers, called shelving buffers, in front of each EU. The design space of shelving is shown in the figure. It consists of the following four main components such as the scope of shelving, the layout of shelving buffers used, the operand fetches policy and the instruction dispatch scheme.Scope of ShelvingThe scope of shelving specifies whether shelving is restricted to multiple instruction types or is performed for all instructions. Partial scheduling is only used in a few superscalar processors. ... Read More

VLIW ArchitectureVLIW represents a Very long instruction word. It is an instruction set architecture constructed to take complete benefit of instruction-level parallelism (ILP) for upgraded performance.Central processing unit processors enable programs to designate instructions to execute in order only whereas a VLIW processor enables programs to explicitly determine instructions to implement in parallel. This design is designed to enable higher implementation without the complexity inherent in some different designs.VLIW architectures are closely associated with superscalar processors. Both objectives at speeding up computation with the aid of exploiting instruction-level parallelism. Both have almost a similar execution basis, including various execution units ... Read More