The Wisconsin multicube architecture employs row and column buses constructing a two-dimensional grid structure as shown in the figure. The three-dimensional generalization will appear in a cube structure.It can describe the cache coherence protocol of the Wisconsin multicube architecture, the following definitions must be given −Possible state of blocks in memoriesUnmodified − The value in the main memory is correct and it can have several correct cache copies.Modified − The value in the main memory is stale and there exists exactly one correct cache copy.Possible state of blocks in cachesData blocks in a particular cache can have three different local ... Read More

Software-based approaches define a good and competitive concession because they need virtually negligible hardware support and they can lead to a similarly limited number of invalidation failures as the hardware-based protocols. All the software-based protocols depend on compiler support. The design space of software-based protocols is shown in the figure.The simplest method is indiscriminate invalidation in which the total cache is invalidated at the end of each programming method. This scheme needs a single hardware structure for passing on or off and invalidating the cache.Selective invalidation schemes can be classified as per the generation of programs methods −The critical method ... Read More

The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high-implementation multiprocessors. It can be providing a cache-coherent-memory model extensible to systems with up to 64K nodes. This Scalable Coherent Interface (SCI) will amount to a peak bandwidth per node of 1 GigaByte/second.The major purpose of the SCI standard is to provide a memory-address-based, cache-coherent communication scheme for creating scalable parallel machines with a large number of processors. The SCI coherency protocol supports a scalable linked list design of distributed directories.The cache mechanism ensures a simultaneously linked list of modifications by all the processors in a shared ... Read More

Directory schemes selectively send consistency commands only to those caches where the valid copy of the shared data block is stored. A directory entry must be associated with each data block. The directory entry consists of a set of pointers to the caches holding a valid copy of the block. A dirty bit specifies if any of the holding caches has the right to update the associated block of data.Three main methods that can be well-known in the recognition of directory schemes are as follows −Full map directory schemeIn the full-map directory scheme, each directory entry consists of as many ... Read More

Snoopy cache protocols are very popular in shared bus multiprocessors due to their relative simplicity. They have both write-update and write-invalidate policy versions. Write-invalidate snoopy cache protocols resemble this protocol in many ways and therefore are also easy to understand after studying a write-update protocol.The definition of transmission routes of commands can be omitted in snoopy cache protocols since the commands are uniformly broadcasted on the shared bus. The protocol applies both the write-back and the write-through update policies. The former is used for private blocks, the latter for shared blocks.The description of possible states of blocks in caches. It ... Read More

Hardware-based protocols support general solutions to the issues of cache coherence without any condition on the cachability of data. Hardware-based protocols can be classified as follows −Memory update policy − There are two types of memory update policy are used in multiprocessors. The write-through policy maintains consistency between the main memory and caches; that is when a block is updated in one of the caches it is immediately updated in memory, too. The write-back policy permits the memory to be temporarily inconsistent with the most recently updated cached block.The application of the write-through policy leads to unnecessary traffic on the ... Read More

In multistage network-based shared memory systems, thousands of processors can try for a similar memory location. This location is called a hotspot and can significantly enlarge latency in the interconnection network. When two processors attempt to access the same memory location, their message will conflict in one of the switches no matter which interconnection network is used (crossbar or multistage). They come at two multiple inputs to the switch but need to exit at the equivalent output.Queuing Network temporarily influences the second message in the switch by using a queue store able to hold a short number of messages. Despite ... Read More

The limited bandwidth of the single shared bus represents a major limitation in building scalable multiprocessors. There are several ways to increase the bandwidth of the interconnection network. A natural idea is to multiply the number of buses, like the processors and memory units. Four different ways have been proposed for connecting buses to the processors, memory units and other buses are as follows −1-dimensional multiple bus system − The simplest generalization of the single bus system towards a multiple bus system is the 1-dimension multiple bus system as shown in the figure. This approach leads to a typical uniform ... Read More

Arbiter logic plays a crucial act in the implementation of pended and split-transaction buses. These are the so-called 1 of N arbiters since they grant the requested resource only to one of the requesters. The design space of arbiter logic is very rich. There are two ways to organize the arbitration logic according to the distribution of its components in the multiprocessor system −Centralized arbiterDecentralized arbiterThe implementation of the fixed priority policy is very simple but it cannot provide a fair allocation of the bus. The highest priority can be dynamically changed in the rotating priority scheme, providing a fair ... Read More

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines are called arbitration lines and play a crucial role in the implementation of shared buses.Secondly, the shared bus is a very cost-effective interconnection scheme. It can be raising the number of processors does not improve the price of the shared bus. However, the contention on the shared bus represents a ... Read More