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Microprocessor Articles
Page 41 of 42
Instruction type DCR R in 8085 Microprocessor
In 8085 Instruction set, DCR is a mnemonic, which stands for ‘DeCRement’ and ‘R’ stands for any of the following registers, or memory location M pointed by HL pair. R = A, B, C, D, E, H, L, or M This instruction is used to decrease the content of register R. Also we can say it will subtract 1 from the register R content. And the decremented value will be stored on to the register R itself. As it is an arithmetic instruction, so all flags, except Cy flag, are affected depending on the result. In those assembly ...
Read MoreInstruction type DCX rp in 8085 Microprocessor
In 8085 Instruction set, DCX is a mnemonic that stands for “DeCrementeXtended register” and rp stands for register pair. And it can be any one of the following register pairs − rp = BC, DE, or HL This instruction will be used to subtract 1 from the present content of the rp. And thus the result of the decremented content will remain stored in rp itself. Though, it is an arithmetic instruction, note that flags are not at all affected by the execution of this instruction. A register pair is generally used to store 16-bit memory address. If ...
Read MoreInstruction type SBB R in 8085 Microprocessor
In 8085 Instruction set, SBB R is mnemonic used for multi-Byte subtraction. Let us consider the following example on such subtraction In this above example, the subtraction of 62H and F1H will result in 71H with a borrow of 1. Next, we have to subtract 44H and 13H along with this borrow value of 1. In the above tracing we have shown you how the internal calculations are being done. Now in 8085, to facilitate such an operation, SBB instruction has been provided to subtract two numbers along with the borrow value. SBB is a mnemonic that stands for ...
Read MoreInstruction type ANA R in 8085 Microprocessor
In 8085 Instruction set, ANA is a mnemonic, which stands for “ANd Accumulator” and “R” stands for any one of the following registers, or memory location M pointed by HL pair. R = A, B, C, D, E, H, L, or M This instruction is used to AND contents of R with Accumulator’s content. The result thus produced for this AND operation will be stored back in to the Accumulator over writing its previous content. As R can have any of the eight values, there are eight opcodes for this type of instruction. It occupies only 1-Byte in ...
Read MoreInstruction type DAD rp in 8085 Microprocessor
In spite of the fact that 8085 is an 8-bit microprocessor, but there are some instructions are there available in the 8085 instruction set which can do 16-bit additions also. As the 8085 internal architecture is only 8-bits, this instruction easily takes double the time needed to add two 8-bit numbers. Here, DAD is a mnemonic, which stands for Double ADd and also rp stands for any one of the following register pairs as mentioned below. rp = BC, DE, or HL As rp can have any of the three values, there are three opcodes for this type ...
Read MoreInstruction type ORA R in 8085 Microprocessor
In 8085 Instruction set, ORA is a mnemonic, which stands for “OR Accumulator” and “R” stands for any of the following registers, or memory location M pointed by HL pair. R = A, B, C, D, E, H, L, or M This instruction is used to OR contents of R with the Accumulator. The result of OR operation will be stored back in the Accumulator. As R can have any of the eight values, there are eight opcodes for this type of instruction. It occupies only 1-Byte in memory. Mnemonics, Operand Opcode(in HEX) Bytes ...
Read MoreInstruction type XRA R in 8085 Microprocessor
In 8085 Instruction, XRA is a mnemonic that stands for “eXclusive OR Accumulator” and “R” stands for any of the following registers, or memory location M pointed by HL pair. R = A, B, C, D, E, H, L, or M This instruction is used to Ex-OR contents of R with the Accumulator. The result of Ex-OR operation will be stored in the Accumulator. As R can have any of the eight values, there are eight opcodes for this type of instruction. It occupies only 1-Byte in memory. Mnemonics, Operand Opcode(in HEX) Bytes ...
Read MoreInstruction type CMC in 8085 Microprocessor
In 8085 Instruction set, CMC stands for “CoMplement the Carry flag”. It performs complement operation on the cy flag, and the result is stored back in the cy flag. Mnemonics, Operand Opcode(in HEX) Bytes CMC 3F 1 The result of execution of this instruction has been depicted in the following tracing table − Before After (Cy) 1 0 Address Hex Codes Mnemonic Comment 2001 3F CMC Complement of Cy when Cy=1 The timing diagram against this instruction CMC execution is as follows − Summary − So this instruction CMC requires 1-Byte, 1-Machine Cycle (Opcode Fetch) and 4 T-States for execution as shown in the timing diagram.
Read MoreInstruction type SPHL in 8085 Microprocessor
In 8085 Instruction set, SPHL is an instruction with the help of which Stack Pointer will get initialized with the contents of register pair HL. It is an indirect way of initializing the stack pointer. But it is not a very common and regularly usable instruction as well. It occupies only 1-Byte in memory, compared to the other instruction LXI SP instruction, which is 3-Bytes long used for initializing SP on the other hand. Due to this advantage, SPHL can be useful when SP is required to get initialized to a specific value a number of times in a program. ...
Read MoreInstruction type CMP R in 8085 Microprocessor
In 8085 Instruction set, CMP is a mnemonic that stands for “CoMPareAccumulator” and hereR stands for any of the following registers, or memory location M pointed by HL pair. R = A, B, C, D, E, H, L, or M This instruction is used to compare contents of the Accumulator with given register R. The result of compare operation will be stored in the Temp register. Temp is not a GPR (General Purpose Register) but an internal register that is not accessible to the programmer. Actually R register’s content will get subtracted from Accumulators content and difference value ...
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