This scheme employs a more cache, known as the branch target address cache (BTAC), for speeding up access to branch targets as shown in the figure. The BTAC includes a group of currently used branch addresses and branch target addresses and is accessed relatively.When the actual instruction fetch address is a branch address, and there is an equivalent entry in the BTAC, the branch target address is fetched along with the branch instruction in a similar cycle. This BTA is then used to access the branch target instruction in the next cycle.The Branch Target Address Cache (BTAC) includes branch target ... Read More

This scheme is the common approach to accessing branch targets. First, the branch target address (BTA) is evaluated either by the pipeline or by a dedicated adder. Thus, the matching branch target instruction (BTI) is fetched. In current processors, this defines access to the I-cache, whereas in initial pipelined processors without an I-cache, the memory is accessed.As shown in the figure, bits go into the details of the compute/fetch scheme. The instruction fetch address (IFA) is maintained in the instruction fetch address register (IFAR), which is usually called the Program Counter (PC) in a sequential environment. It can start the ... Read More

There are two basic tasks to be implemented the discard the results of the speculative execution and resume execution of the alternative, that is, the true path as shown in the figure.When there is higher than one pending conditional branch, the corresponding alternative path should be chosen and followed. In recovery from a mispredicted taken path, as preparation for a possible recovery from a misprediction, the processor has to store the address of the sequential preservation, before it initiates execution of the guessed taken path. The recovery phase can be minimized if previously prefetched sequential instructions are not discarded but ... Read More

A processor extends to execute instructions speculatively until the condition is resolved. The time interval between the beginning of the conditional execution and the resolution of the equivalent condition can change significantly. The condition is resolved the immediately following cycle.This appears when the specified condition defines the result of a simple operation, including integer addition, subtraction, or logical operation. In the case of long operations, including FX or FP division, multiple cycles will pass earlier the condition can be resolved.The superscalar processor can issue several instructions in each cycle. Thus, during speculative execution scores of instructions are executed before the ... Read More

History bits are used to record branch history. Processors employ one of the four different schemes to implement history bits as shown in the figure. In the most straightforward scheme history bits are placed in the I-cache.For instance, the α processors provide one (21064) or two (21064A) history bits in the I-cache for each instruction. In contrast, the UltraSparc maintains only two 2-bit entries for each cache line, which contains four instructions. The Sparc architecture maintains delay slots, thus not more than two branches (and two delay slots) can occur in four subsequent instructions.In the PowerPC 604, there is a ... Read More

There are two different approaches for expressing the history of branches as shown in the figure. In the explicit dynamic technique, branch history is explicitly stated in the form of history bits. The actual implementation of this technique using one, two, or three bits for expressing the history. The second approach is the implicit dynamic technique, in which branch history is implicitly stated by the existence of an entry for a predicted branch target access path.1-bit dynamic prediction − This is the simplest dynamic technique. In a 1-bit prediction, a single bit per branch can define whether the final occurrence ... Read More

In a static prediction technique, the branch is ‘always taken’ or the branch is ‘always not-taken’ approaches. It can make static predictions by investigating particular attributes of the object code. In actual implementation, static predictions are either opcode-based, displacement-based, or based on a hint delivered by the compiler, as shown in the figure.Opcode-based predictions are made by assuming that the branch will be ‘taken’ for certain opcodes and ‘not taken’ for others. This prediction technique is used, for instance, in the MC 88110 and PowerPC 601/603 processors. As shown in the table, shows how opcode-based prediction is accomplished in the ... Read More

In a fixed prediction a similar guess is continually made, either ‘always taken’ or ‘always not-taken’ approaches.‘Always not-taken approach’ − The ‘always not taken’ approach (or ‘not taken’ approach for short) has the following typical processing scheme are as follows −It can detect an unresolved conditional branch and guess it as not taken’.It can continue with the execution of the sequential path, but in preparation for a wrong guess, start the execution of the taken path (for example, calculate BTA) in parallel.When the condition becomes evaluable, check the guess.If the guess is correct, continue with the execution of the sequential ... Read More

The branch prediction scheme used in a processor has a central impact on its execution. Therefore, some effort has been placed into promoting an effective scheme.A prediction can be a fixed or a true prediction. In a fixed prediction the same guess is continually made, either ‘taken’ or ‘not-taken’. This is a one outcome guess. The ‘always not taken’ approach prefers the ‘not taken’ path, so the taken penalty (TP) is typically higher than the not-taken penalty (NTP).The ‘not-taken’ scheme is easier to implement than the ‘taken’ scheme. A large number of pipelined microprocessors employ this scheme, including certain earlier ... Read More

A conditional branch cannot be computed earlier than the referenced conditional is known. For instance, if the specified condition defines the sign of the outcome of the previous instruction, the precondition of the computation is that the previous instruction has been performed.Until the referenced condition will become known, the conditional branch is stated to unresolved. There are three basic elements utilized by processors to cope with unresolved conditional branches such as blocking branch processing, speculative execution, and multiway branching, as shown in the figure −Blocking branch processing is the trivial element to cope with unresolved conditional branches. Execution of the ... Read More