Linear Pipeline ProcessorLinear pipelining is an approach that decomposes any sequential process into limited subprocesses, which are separate from each other so that every subprocess can be implemented in a unique dedicated segment and all these segments work concurrently. Thus the whole function is divided into separate tasks and these subtasks are implemented by a segment.The concept of pipelining in computer architecture is corresponding to a technical assembly line. As in the market there multiple divisions like manufacturing, packing, and delivery division, a product is manufactured by the manufacturing division, while it is packed by the packing division a new ... Read More

Virtual memory is the partition of logical memory from physical memory. This partition supports large virtual memory for programmers when only limited physical memory is available.Virtual memory can give programmers the deception that they have a very high memory although the computer has a small main memory. It creates the function of programming easier because the programmer no longer requires to worry about the multiple physical memory available.Virtual memory works similarly, but at one level up in the memory hierarchy. A memory management unit (MMU) transfers data between physical memory and some gradual storage device, generally a disk. This storage ... Read More

DMA represents Direct Memory Access. It is a hardware-controlled data transfer method. An external device can control data transfer. The external device creates address and control signals that are needed to control data transfer. External devices also enable peripheral devices to directly access memory. The external device which controls the data transfer is known as the DMA controller.There are three different modes of DMA data transfer which are as follows −Burst Mode − In burst mode, a whole block of data is shared in one contiguous sequence. Since the DMA controller is allowed access to the system buses by the ... Read More

Segmentation is another approach of allocating memory that can be used rather than or in conjunction with paging. In its purest form, a program is broken into multiple segments, each of which is a self-contained unit, including a subroutine or data structure.Unlike pages, segments can vary in size. This requires the MMU to manage segmented memory somewhat differently than it would manage paged memory. A segmented MMU contains a segment table to maintain track of the segments resident in memory.A segment can create at one of many addresses and can be of any size, each segment table entry should contain ... Read More

Paging is a storage structure that enables the operating framework to fetch processes from the secondary storage into the main memory in the form of pages. In the Paging method, the main memory is split into small fixed-size blocks of physical memory, which is known as frames. The size of a frame must be preserved the same as that of a page to have maximum use of the main memory and to prevent external fragmentation.Paging changes pages from the swap disk to frames of the physical memory therefore data can be accessed by the processor. Any page can involve any ... Read More

The main reason for containing cache memory in a computer is to increase system performance by decreasing the time required to access memory. The component of cache performance are cache hits and cache misses.Each time the CPU accesses memory, it determines the cache. If the requested data is in the cache, the CPU accesses the data in the cache, instead of physical memory, this is a cache hit. If the data is not in the cache, the CPU accesses the data from the main memory. This is a cache miss.The average memory access time, TM is the weighted average of ... Read More

IEEE developed the IEEE 754 floating-point standard. This standard defines set formats and operation modes. All computers conforming to this standard would always calculate the same result for the same computation. This standard does not specify arithmetic procedures and hardware to be used to perform computations. For example, a CPU can meet the standard whether it uses shift-add hardware or the Wallace tree to multiply two significant.The IEEE 754 standard specifies two precisions for floating-point numbers. Single precision numbers have 32 bits − 1 for the sign, 8 for the exponent, and 23 for the significand. The significand also includes ... Read More

In this section, there are two ways to take advantage of this redundancy to reduce the number of microinstructions needed by the control unit. The first method uses microsubroutines to combine repeated micro-operations into a single block of micro-instructions, which are accessed by two or more execute routines. The other method uses microcode jump to access microinstruction shared by two or more routines.MicrosubroutinesJust as high-level and assembly language codes use subroutines, a microsequencer can also use microsubroutines. As with high-level code, a microsequencer uses microsubroutines for sequences of actions that are performed in more than one routine in a microcode. ... Read More

In vertical microcode, each microinstruction is encoded i.e., the bit field can pass through intermediate combinatory logic which in turn creates the actual control signals for internal CPU components (ALU, registers, etc). In vertical microcode, the micro-operations are grouped into fields such that no more than one micro-operation in a field is active during any state. Then a unique field value is assigned to each micro-operation in the field.For example, a field with eight different micro-operations would require 3 bits, each value from 000 to 111 would be assigned to one of the eight micro-operations. The micro-operation field bits are ... Read More

In horizontal microcode, each micro-operation is represented by one bit in each microinstruction. Horizontal microcode is generally included in a fairly wide control save it is not exceptional for each work to be 56 bits or more. On each click of a sequencer clock, a microcode word is read, decoded, and used to control the functional components which create up the CPU. The micro-operations and their mnemonics are shown in the table.Microoperations and their mnemonics for the very simple CPUMnemonicMicro-OperationARPCAR←PCARDRAR←DR[5….0]PCINPC←PC+1PCDRPC←DR[5…0]DRMDR←MIRDRIR←DR[7…6]PLUSAC←AC+DRANDAC←AC ^ DRACINAC←AC+1Since there are nine micro-operations, each word of microcode requires 9 bits to represent them, 1 bit per micro-operation. ... Read More