In a fixed prediction a similar guess is continually made, either ‘always taken’ or ‘always not-taken’ approaches.‘Always not-taken approach’ − The ‘always not taken’ approach (or ‘not taken’ approach for short) has the following typical processing scheme are as follows −It can detect an unresolved conditional branch and guess it as not taken’.It can continue with the execution of the sequential path, but in preparation for a wrong guess, start the execution of the taken path (for example, calculate BTA) in parallel.When the condition becomes evaluable, check the guess.If the guess is correct, continue with the execution of the sequential ... Read More

The branch prediction scheme used in a processor has a central impact on its execution. Therefore, some effort has been placed into promoting an effective scheme.A prediction can be a fixed or a true prediction. In a fixed prediction the same guess is continually made, either ‘taken’ or ‘not-taken’. This is a one outcome guess. The ‘always not taken’ approach prefers the ‘not taken’ path, so the taken penalty (TP) is typically higher than the not-taken penalty (NTP).The ‘not-taken’ scheme is easier to implement than the ‘taken’ scheme. A large number of pipelined microprocessors employ this scheme, including certain earlier ... Read More

A conditional branch cannot be computed earlier than the referenced conditional is known. For instance, if the specified condition defines the sign of the outcome of the previous instruction, the precondition of the computation is that the previous instruction has been performed.Until the referenced condition will become known, the conditional branch is stated to unresolved. There are three basic elements utilized by processors to cope with unresolved conditional branches such as blocking branch processing, speculative execution, and multiway branching, as shown in the figure −Blocking branch processing is the trivial element to cope with unresolved conditional branches. Execution of the ... Read More

A branch in a computer program is an instruction that communicates a device to start implementing several instructions instead of easily performing the instructions in order. In high-level languages, these are defined as flow control phases and are established into the language. The figure shows an overview of branch detection methods employed in microprocessors.Early pipelined microprocessors detect branches during the common instruction decoding (master pipeline approach). The disadvantage of this straightforward technique is that it provides rise to Long Branch processing penalties. It can reduce taken penalties, up-to-date processors generally detect branches previous than during common instruction coding (early branch ... Read More

Branch processing has two methods, such as the layout of branch processing and its microarchitectural implementation of branch processing, as shown in the figure. Branch processing consists of three major subtasks such as the detecting branches, handling unresolved conditional branches, and accessing the branch target path.The first aspect is branch detection. Initially, processors detected branches during instruction decoding. However, the earlier a processor identifies branches, the previous branch processing can be initiated and the less penalties there are. Thus, novel schemes try to encounter branches as early as possible.The most advanced technique of branch detection prevents explicit decoding. Instead, branch ... Read More

There are two possible ways of extending the basic concepts such as increasing the multiplicity of delay slots or introduce annulment of instruction in the delay slot. Most architecture provides one delay slot only. Few architectures are offering multiple delay slots, such as the MIPS-X.The other possibility to fill more delay slots is to introduce annulment (also called nullification or squashing). The basic idea is to introduce options in using delay slots, which can permit more delay slots to be filled than in the case of the basic scheme. Four different types of annulment can be introduced. The four variants ... Read More

When branches are processed by a pipeline simply, after each taken branch, at least one cycle remains unutilized. This is because of the assembly line-like apathy of pipelining. Instruction slots following branches are known as branch delay slots.Delay slots can also appear following load instructions; these are defined load delay slots. Branch delay slots are wasted during traditional execution. However, when delayed branching is employed, these slots can be at least partly used.Principle of Delayed branchingtiti+1ti+2ti+3ti+4BbFDEWBAaddFDEWBCsubFDBTAFIn the figure, it can transfer the add instruction of our program segment that initially preceded the branch into the branch delay slot. With delayed ... Read More

Processors use a large variety of approaches and techniques for branch handling. Three methods give an increase to the basic methods of in-branch handling. These are as follows −whether branch delay slots are usedhow unresolved conditional branches are handledwhether the architecture provides represents to prevent conditional branches.The fundamental approaches to branch handling reflect these questions. According to how to branch handling responds to these questions it can determine delayed branching, blocking and speculative branch processing, multiway branching, and guarded execution.The first method is whether branch delay slots are used. The simple branch handling generally results in one or two wasted ... Read More

It can evaluate and compare different branch processing techniques, it can require a performance measure. Let us consider the execution of a branch instruction in a four-stage pipeline as shown in the figure. If the branch is processed straightforwardly, the branch target address (BTA) will be computed in cycle ti+3.Then the branch target instruction can be fetched in cycle ti+4. Thus, the branch target instruction is fetched with a 3 cycles delay in comparison to the fetching of the branch instruction. This means a 2-cycle penalty compared to the sequential processing.The performance of branch processing in a certain typical situation. ... Read More

Pipelining is a very effective method for speeding up instruction execution along a sequential path. But if a branch introduces the pipeline and disorganizes the sequential processing, the implementation of the pipeline will be seriously disrupted unless appropriate methods are used.It can indicate the problems that generate branches in pipelines. Let us suppose the implementation of an unconditional branch in a pipeline. An unconditional branch is implemented on a traditional RISC pipeline when no specific care is taken to boost adaptability.The pipeline is considered to process instructions in four subsequent cycles, such as, in the consecutive fetch (F), decode (D), ... Read More