Branch processing comprises basic tasks, such as instruction fetch, decode and BTA calculation, and possibly additional dedicated tasks to speed up branch processing. These dedicated tasks may be early branch detection, branch prediction, or an advanced scheme for accessing target paths.Usually, the dedicated tasks are executed using dedicated hardware, like a BTAC, BTIC, or BHT. There are two methods to the basic tasks. All earlier pipelined processors and many recent processors execute branches by utilizing the pipeline stages available for common instruction processing as shown in the figure −By contrast, some recent processors provide a separate unit, usually called a ... Read More

This is the latest scheme introduced to access branch targets, employed in a few recently announced processors such as the Am29000 superscalar, K5, and UltraSparc. Here, the basic idea is to append, for each line in the I-cache, a successor index that points to the next line to be fetched as shown in the figure. In all the processors, each cache line can contain 16 bytes of instructions.This means that a cache line holds in the AM29000 superscalar and the UltraSparc four instructions, whereas in the x86-compatible K5 a variable number of CISC instructions. The successor index is fetched in ... Read More

This scheme is only used occasionally, in cases when the taken penalty would be intolerable high due to a longer than I-cache latency. The basic idea of the BTIC scheme is to provide a small extra cache that delivers, for taken or predicted taken branches, the branch target instruction or a specified number of BTIs, rather than the BTA. Thus, otherwise unused pipeline cycles can be filled with target instructions.There are two alternatives implementations of the BTIC scheme, as shown in the figure. In the first, the address of the continuation of the taken path is also stored in the ... Read More

This scheme employs a more cache, known as the branch target address cache (BTAC), for speeding up access to branch targets as shown in the figure. The BTAC includes a group of currently used branch addresses and branch target addresses and is accessed relatively.When the actual instruction fetch address is a branch address, and there is an equivalent entry in the BTAC, the branch target address is fetched along with the branch instruction in a similar cycle. This BTA is then used to access the branch target instruction in the next cycle.The Branch Target Address Cache (BTAC) includes branch target ... Read More

This scheme is the common approach to accessing branch targets. First, the branch target address (BTA) is evaluated either by the pipeline or by a dedicated adder. Thus, the matching branch target instruction (BTI) is fetched. In current processors, this defines access to the I-cache, whereas in initial pipelined processors without an I-cache, the memory is accessed.As shown in the figure, bits go into the details of the compute/fetch scheme. The instruction fetch address (IFA) is maintained in the instruction fetch address register (IFAR), which is usually called the Program Counter (PC) in a sequential environment. It can start the ... Read More

There are two basic tasks to be implemented the discard the results of the speculative execution and resume execution of the alternative, that is, the true path as shown in the figure.When there is higher than one pending conditional branch, the corresponding alternative path should be chosen and followed. In recovery from a mispredicted taken path, as preparation for a possible recovery from a misprediction, the processor has to store the address of the sequential preservation, before it initiates execution of the guessed taken path. The recovery phase can be minimized if previously prefetched sequential instructions are not discarded but ... Read More

A processor extends to execute instructions speculatively until the condition is resolved. The time interval between the beginning of the conditional execution and the resolution of the equivalent condition can change significantly. The condition is resolved the immediately following cycle.This appears when the specified condition defines the result of a simple operation, including integer addition, subtraction, or logical operation. In the case of long operations, including FX or FP division, multiple cycles will pass earlier the condition can be resolved.The superscalar processor can issue several instructions in each cycle. Thus, during speculative execution scores of instructions are executed before the ... Read More

History bits are used to record branch history. Processors employ one of the four different schemes to implement history bits as shown in the figure. In the most straightforward scheme history bits are placed in the I-cache.For instance, the α processors provide one (21064) or two (21064A) history bits in the I-cache for each instruction. In contrast, the UltraSparc maintains only two 2-bit entries for each cache line, which contains four instructions. The Sparc architecture maintains delay slots, thus not more than two branches (and two delay slots) can occur in four subsequent instructions.In the PowerPC 604, there is a ... Read More

There are two different approaches for expressing the history of branches as shown in the figure. In the explicit dynamic technique, branch history is explicitly stated in the form of history bits. The actual implementation of this technique using one, two, or three bits for expressing the history. The second approach is the implicit dynamic technique, in which branch history is implicitly stated by the existence of an entry for a predicted branch target access path.1-bit dynamic prediction − This is the simplest dynamic technique. In a 1-bit prediction, a single bit per branch can define whether the final occurrence ... Read More

In a static prediction technique, the branch is ‘always taken’ or the branch is ‘always not-taken’ approaches. It can make static predictions by investigating particular attributes of the object code. In actual implementation, static predictions are either opcode-based, displacement-based, or based on a hint delivered by the compiler, as shown in the figure.Opcode-based predictions are made by assuming that the branch will be ‘taken’ for certain opcodes and ‘not taken’ for others. This prediction technique is used, for instance, in the MC 88110 and PowerPC 601/603 processors. As shown in the table, shows how opcode-based prediction is accomplished in the ... Read More