UMA represents Uniform memory access. It is a shared memory architecture used in parallel computers. All the processors in the UMA model share the physical memory uniformly. In UMA architecture, access time to a memory location is autonomous of which processor creates the request or which memory chip includes the shared data.Although the UMA architecture is not suitable for building scalable parallel computers, it is excellent for constructing small-size single bus multiprocessors. Two such machines are the Encore Multimax of Encore Computer Corporation representing the technology of the late 1980s and the Power Challenge of Silicon Graphics Computing Systems representing ... Read More

In adaptive routing, intermediate nodes can take the actual network conditions, including the presence of deterioration or bottlenecks, into account and decide accordingly which neighbor the message should be transmitted. Adaptive routing scheme can be either profitable or misrouting according to the selection of the output channel. In profitable routing, only channels that are known to be guaranteed to move closer to the destination are candidates for selection.Profitable routing represents a conservative view. Misrouting protocols rely on an optimistic view and can use both profitable and non-profitable channels for establishing a path between the source and destination. Selecting a non-profitable ... Read More

In deterministic routing, the path is fully determined by the source and destination nodes. Intermediate nodes are unable to direct messages even in the case of network congestion.Deterministic routing can be further classified according to the node position where the deterministic path is selected. In source routing, it is the source node that selects the complete path between the source and destination nodes. Distributed routing gives each intermediate node the freedom to independently determine the next node of the path to which the message should be sent. There are three deterministic routing schemes are as follows −Street-sign routing − Street-sign ... Read More

Switching is the actual mechanism by which a message is removed from the input buffer and placed in the output buffer. The switching technique applied has an over-whelming effect on message latency and hence the choice of switching method is crucial in designing any distributed memory computer. The design space of the switching technique is shown in the figure.Packet Switching (store and forward)In the first-generation multicomputer, the packet switching mechanism was borrowed from the world of computer networks. The packet switching mechanism behaves in a store and forward manner similar to the mail service. A message is divided into packets ... Read More

In a static network, the connection between input and output nodes is fixed and cannot be modified. Static interconnection network cannot be reconfigured. Examples of this network are linear array, ring, chordal ring, tree, star, fat tree, mesh, tours, systolic arrays, and hypercube. The design space for static interconnection topologies is shown in the figure.Linear ArrayThis is a most elementary interconnection design. In this processors are linked in a linear one-dimensional array. The first and last processors are linked with one adjacent processor and the middle processing components are linked with two adjacent processors. It is a one-dimensional interconnection network.RingThis ... Read More

Direct Interconnection networks are used to connect different processing elements or different process memory. Interconnection networks are also known as multi-stage interconnection networks (or MINs), are high-speed computer networks.Characteristics of Direct Interconnection NetworkTopology − It denotes how the nodes of a network are organized.Network Diameter − It is the minimum distance between the most distant nodes in a network. The distance is measured in terms of the multiple specific hops between any two nodes.Node degree − The number of edges linked with a node is known as node degree. If the edge carries information from the node, it is known ... Read More

Shared Memory MIMD Architectures is known as Multiprocessor. It can consider a set of processors and a set of memory modules. Any processor can directly access any memory module through an interconnection network as displayed in the figure. The set of memory modules represent a global address space that is shared by all processors. This type of parallel machine is called Shared Memory MIMD Architectures.Advantages of Shared Memory MIMD ArchitecturesThere are the following advantages of shared memory MIMD architectures are as follows −There is no requirement to partition either the code or the data, thus uniprocessor programming methods can simply ... Read More

Distributed memory MIMD Architecture is known as Multicomputer. It can replicate the processor/memory pairs and link them through an interconnection network. The processor/memory pair is known as the processing element (PE) and PEs work more or less separated from each other.Whenever interaction between them is possible through message passing one PEs cannot directly access the memory of other PE. This class of MIMD machines is known as distributed memory MIMD architectures or message passing MIMD architectures.In distributed-memory MIMD machines, each processor has its memory location. Each processor has no explicit knowledge about other processor's memory. For data to be transmitted, ... Read More

Guarded execution is a means to eliminate; at least partly, conditional branches. The idea is to introduce conditional operate instructions into the architecture and use them to replace conditional branches. Conditional operate instructions are called guarded instructions. A guarded instruction consists of two parts, a conditional part called the guard and an operational part which is a traditional instruction. It can be expressed, for instance, in the form −(guard) instructionThe execution of guarded instruction depends on the following condition: if the specified guard is true, the associated instruction will be executed; if the guard turns out to be false, the ... Read More

Multiway branching is another possibility for reducing branch penalties. With multiway branching, both the sequential and the taken paths of an unresolved conditional branch are pursued, as shown in the figure. The multiway branching requires multiple program counters (PCs) referred to as IFA1 and IFA2 in the figure.Once the specified condition is resolved, which of the paths is correct becomes evident. If the correct path is the sequential one, its execution will be confirmed and the taken path execution discarded, consequently, IFA1 contains the correct continuous address. In the opposite case, vice versa.During speculative execution of a conditional branch, a ... Read More