Hardware-based protocols support general solutions to the issues of cache coherence without any condition on the cachability of data. Hardware-based protocols can be classified as follows −Memory update policy − There are two types of memory update policy are used in multiprocessors. The write-through policy maintains consistency between the main memory and caches; that is when a block is updated in one of the caches it is immediately updated in memory, too. The write-back policy permits the memory to be temporarily inconsistent with the most recently updated cached block.The application of the write-through policy leads to unnecessary traffic on the ... Read More

In multistage network-based shared memory systems, thousands of processors can try for a similar memory location. This location is called a hotspot and can significantly enlarge latency in the interconnection network. When two processors attempt to access the same memory location, their message will conflict in one of the switches no matter which interconnection network is used (crossbar or multistage). They come at two multiple inputs to the switch but need to exit at the equivalent output.Queuing Network temporarily influences the second message in the switch by using a queue store able to hold a short number of messages. Despite ... Read More

The limited bandwidth of the single shared bus represents a major limitation in building scalable multiprocessors. There are several ways to increase the bandwidth of the interconnection network. A natural idea is to multiply the number of buses, like the processors and memory units. Four different ways have been proposed for connecting buses to the processors, memory units and other buses are as follows −1-dimensional multiple bus system − The simplest generalization of the single bus system towards a multiple bus system is the 1-dimension multiple bus system as shown in the figure. This approach leads to a typical uniform ... Read More

Arbiter logic plays a crucial act in the implementation of pended and split-transaction buses. These are the so-called 1 of N arbiters since they grant the requested resource only to one of the requesters. The design space of arbiter logic is very rich. There are two ways to organize the arbitration logic according to the distribution of its components in the multiprocessor system −Centralized arbiterDecentralized arbiterThe implementation of the fixed priority policy is very simple but it cannot provide a fair allocation of the bus. The highest priority can be dynamically changed in the rotating priority scheme, providing a fair ... Read More

One of the most famous interconnection networks is the single shared bus. Firstly, its organization is simply a generalization and extension of the buses employed in uniprocessors and some additional ones to solve the contention on the bus when several processors simultaneously want to use the shared bus. These lines are called arbitration lines and play a crucial role in the implementation of shared buses.Secondly, the shared bus is a very cost-effective interconnection scheme. It can be raising the number of processors does not improve the price of the shared bus. However, the contention on the shared bus represents a ... Read More

COMA stands for Cache-only memory access machines. A COMA machine includes several processing nodes connected by an interconnection network. Each processing node has a high-implementation processor, a cache, and an allocation of the global shared memory.COMA machines try to avoid the problems of static memory allocation of NUMA and CC-NUMA machines by excluding main memory blocks from the local memory of nodes and employing only large caches as node memories. In these architectures only cache memories are present; no main memory is employed either in the form of a central shared memory as in UMA machines or the form of ... Read More

CC-NUMA stands for Cache-coherent non-uniform memory access machines. A CC-NUMA machine includes several processing nodes linked through a high-bandwidth low-latency interconnection network. Each processing node includes a high-implementation processor, the related cache, and an allocation of the global shared memory.Cache coherence is preserved by a directory-based, write-invalidate cache coherence protocol. It can maintain all caches consistent, every processing node has a directory memory corresponding to its allocation of the shared physical memory.For each memory line, the directory memory saves recognizes remote nodes caching that line. Thus, utilizing the directory, it is applicable for a node writing a location to send ... Read More

Cray T3D is the most recent NUMA machine that was designed to provide a highly scalable parallel supercomputer that can incorporate both the shared memory and the message-passing programming paradigms. As in other NUMA machines, the shared memory is distributed among the processing elements to avoid the memory access bottleneck and there is no hardware support for cache coherency. However, a special software package and programming model, called the CRAFT, manages coherence and guarantees the integrity of the data.The Cray T3D hardware structure is divided into three parts are as follows −MicroarchitectureMacroarchitectureThe microarchitecture is based on Digital’s 21064 Alpha AXP ... Read More

Hector is a hierarchical NUMA machine consisting of stations connected by a hierarchy of ring networks. Stations are symmetric multiprocessors where the processing modules are linked by an individual bus. Nodes comprise three main units − a processor/cache unit, a memory unit, and the station bus interface which connects the otherwise separated processor and memory buses.The separation of two bus enables other processors to access this memory while the processor performs memory access operations in off-node memory. The processing modules of the machine are grouped into shared bus symmetric multiprocessors, called stations. These are connected by bit-parallel local rings, which ... Read More

NUMA represents Non-uniform Memory Access. NUMA is a multiprocessor model in which each processor is connected with the dedicated memory. Non-uniform memory access (NUMA) machines were intended to prevent the memory access bottleneck of UMA machines. The logically shared memory is physically assigned among the processing nodes of NUMA machines, leading to distributed shared memory architectures.These parallel computers became hugely scalable, but they are very responsive to data allocation in local memories. Accessing a local memory segment of a node is much quicker than accessing a remote memory segment.The main difference is in the organization of the address space. In ... Read More