EncoderA digital circuit that executes the inverse services of a decoder is known as an encoder. It has 2n input lines and n output lines. In an encoder, the output lines create the binary code equivalent to the input value. The figure displays the general architecture of an encoder circuit.DecoderThe decoder is an electronic device that can modify a digital signal to an analog signal. It enables a single input line and creates multiple output lines. The decoders are used in several communication projects that are connected between two devices. The decoder enables N- inputs and creates 2 power N-numbers ... Read More

Classic mask-programmed ROM chips are joined circuits that physically encode the information to be saved, and therefore it is inaccessible to modify their contents after fabrication. Several methods of non-volatile solid-state memory allow some degree of modification −Programmable read-only memory (PROM) − It is a one-time programmable ROM (OTP) and can be written to or programmed through a unique device known as a PROM programmer. This device uses high voltages to permanently damage or generate internal connections (fuses or anti-fuses) inside the chip.Erasable Programmable read-only memory (EPROM) − It can be erased by hazard to powerful ultraviolet light (generally for ... Read More

RAM is an element of the main memory that is directly usable by the CPU (Central Processing Unit). Memory can save programs and information during computer operations. The major technology used for the main memory depends on semiconductor integrated circuits.The feature of RAM is that it is volatile. A RAM should be supported with a fixed power supply. If the power is disrupted, therefore the data is hidden. Therefore, RAM can be used only as temporary storage. RAM technology has been divided into technologies which are as follows −Static RAM − Memories that include circuits that are adequate for maintaining ... Read More

MultiplexerA multiplexer is a combinational circuit that obtains binary data from one of 2" input data lines and manages it to an individual output line. The selection of a specific input data line for the output is decided by a collection of selection inputs. A 2"-to-1 multiplexer has 2" input data lines and n input selection lines whose bit combinations decide which input data are chosen for the output.Multiplexing is a procedure and method of transmitting multiple analog or digital input signals or data flow over one route. Multiplexing organizes multi-low-speed medium into one high-speed route for transmission, the high-speed ... Read More

Convex was the first device produce to commercialize a CC-NUMA machine, known as the SPP1000. SPP represents a Scalable Parallel Processor. The goals of the SPP Exemplar series are to make a family of high-implementation computers where the multiple processors can simply range from 10 to 1000 and the peak implementation would arrive at the TeraFLOPS.The node of the SP1000 is symmetric multiprocessors, called hyper nodes. Each hypernode includes four functional blocks and an I/O subsystem. Each functional block includes two CPUs (HP PA-RISCs) sending an individual CPU agent, and a memory unit influencing hypernode private memory data, global memory ... Read More

The Wisconsin multicube architecture employs row and column buses constructing a two-dimensional grid structure as shown in the figure. The three-dimensional generalization will appear in a cube structure.It can describe the cache coherence protocol of the Wisconsin multicube architecture, the following definitions must be given −Possible state of blocks in memoriesUnmodified − The value in the main memory is correct and it can have several correct cache copies.Modified − The value in the main memory is stale and there exists exactly one correct cache copy.Possible state of blocks in cachesData blocks in a particular cache can have three different local ... Read More

Software-based approaches define a good and competitive concession because they need virtually negligible hardware support and they can lead to a similarly limited number of invalidation failures as the hardware-based protocols. All the software-based protocols depend on compiler support. The design space of software-based protocols is shown in the figure.The simplest method is indiscriminate invalidation in which the total cache is invalidated at the end of each programming method. This scheme needs a single hardware structure for passing on or off and invalidating the cache.Selective invalidation schemes can be classified as per the generation of programs methods −The critical method ... Read More

The Scalable Coherent Interface (IEEE P1596) is establishing an interface standard for very high-implementation multiprocessors. It can be providing a cache-coherent-memory model extensible to systems with up to 64K nodes. This Scalable Coherent Interface (SCI) will amount to a peak bandwidth per node of 1 GigaByte/second.The major purpose of the SCI standard is to provide a memory-address-based, cache-coherent communication scheme for creating scalable parallel machines with a large number of processors. The SCI coherency protocol supports a scalable linked list design of distributed directories.The cache mechanism ensures a simultaneously linked list of modifications by all the processors in a shared ... Read More

Directory schemes selectively send consistency commands only to those caches where the valid copy of the shared data block is stored. A directory entry must be associated with each data block. The directory entry consists of a set of pointers to the caches holding a valid copy of the block. A dirty bit specifies if any of the holding caches has the right to update the associated block of data.Three main methods that can be well-known in the recognition of directory schemes are as follows −Full map directory schemeIn the full-map directory scheme, each directory entry consists of as many ... Read More

Snoopy cache protocols are very popular in shared bus multiprocessors due to their relative simplicity. They have both write-update and write-invalidate policy versions. Write-invalidate snoopy cache protocols resemble this protocol in many ways and therefore are also easy to understand after studying a write-update protocol.The definition of transmission routes of commands can be omitted in snoopy cache protocols since the commands are uniformly broadcasted on the shared bus. The protocol applies both the write-back and the write-through update policies. The former is used for private blocks, the latter for shared blocks.The description of possible states of blocks in caches. It ... Read More