Intel 8259 is designed as a 28-pin-programmable IC available as a package named DIP (Dual inline package). Its physical and functional pin diagrams are indicated below.PIN NameDescription and PurposesVcc and GndIt is the Power supply and ground pins. +5V power supply isused in this chip.D7-0For communication with the processor, there are Eight bi-directional data pins.RD*It is active low-input pin activated by the processor to read the information status from the 8259.WR*It is an active low-input pin which is activated by the processor to write the control information to  8259.CS*For selecting the chip it is used an active low input pin.A0An ... Read More

8259 Microprocessor is architected in a unique style. It can program by means of some interrupts conditions by means of level or interrupt level often called edge-triggered interrupt level. Masking is done to individual interrupt bits. As the number of 8259 increases interrupt pins up to 64 can be obtained. There are 3 registers 8259 contains along with one priority resolver(PR). They are as follows −Interrupt Request Register(IIR)  − It stores the bits who requests the interrupt.Interrupt service register(ISR) − It stores the currently interrupt levels.Interrupt Mask Register(IMR)  − Stores the interrupt levels to be masked.PriorityResolver(PR)  − Set the priority of ... Read More

The interrupt requests are accepted by 8259 from many interrupting devices IR0 to IR7  pins. After that, it identifies the highest priority interrupt request from those inputs that are already active. To configure the 8259 for fixed priority mode of operation, among them IR0 has the highest and IR7 has the lowest priority. If the inputs IR2, IR4, and IR6 are active, thenIR2 has the highest priority interrupt request among the active requests than the other. The details of the interrupt requests those are active are stored in the Interrupt Request Register (IRR).By loading the Interrupt Mask Register (IMR), it ... Read More

8085 microprocessor, consists of five interrupt input pins named as RST 5.5, RST 6.5, RST7.5, INTR, and TRAP respectively. When there are a maximum of five I/O devices they want to perform driven interrupt data transfer, which is connected to the five interrupt input pins. Now considering the case where there are more than five I/O devices which would like to perform an interrupt driven data transfer scheme. Here for some pins termed as an interrupt, we use more than one I/O device to the process. Most of the microprocessors nowadays have the configuration of these interrupt input pins. There ... Read More

In 8085 Instruction set, there is one mnemonic XCHG, which stands for eXCHanGe. This is an instruction to exchange contents of HL register pair with DE register pair. This instruction uses implied addressing mode. In the instruction, we don’t mention as “XCHG HL, DE”. It is implied that it will deal with HL and DEregister pairs. So we write only XCHG as mnemonic. That’s why it is called an implied addressing mode. As it is 1-Byte instruction, so It occupies only 1-Byte in the memory. After execution of this instruction, the content between H and D registers and L and ... Read More

In this mode, the data is transferred from one register to another by using the address pointed by the register. Register indirect addressing mode also used to call as indirect addressing mode. For example MOV A, M: means data is transferred from the memory address pointed by the register pair HLto the register A.MOV E, MIt occupies only 1-Byte in memory. MOV E, M is an example instruction of this type. It is a 1-Byte instruction. Suppose E register content is DBH, H register content is 40H, and L register content is 50H. Letus say location 4050H has the data ... Read More

In this mode, the data is directly copied from the given address to the register. This absolute addressing mode is also called a direct addressing mode. For example LDA 3000H: means the data at address 3000H is copied to register A.LDA 4050HLet us consider LDA 4050 Has an example instruction of this type. It is a 3-Byte instruction. The initial content of memory address 4050H is ABH. initial accumulator content is CDH. As after execution A will be initialized with value ABH. Memory location 4050H will still remain with the content ABH. The results of the execution of this instruction ... Read More

In this mode, the data is copied from one register to another. For example, MOV A, B: means data in register B is copied to register A.MOV E, HIt occupies only 1-Byte in memory. MOV E, H is an example instruction of this type. It is a 1-Byte instruction. Suppose E register content is AB H, and H register content is 9C H. When the 8085 executes this instruction, the contents of E register will change to 9C H.This is shown as follows.BeforeAfter(E)ABH9CH(H)9CH9CHAddressHex CodesMnemonicComment20045CMOV E, HE ← HNote that H register’s content has not been changed at all. Although Intel has called ... Read More

In this mode, the 8/16-bit data is specified in the instruction itself as one of its operand. For example MVI E, ABH: means ABH is copied into register A. Here the operand is immediately available in the instruction.MVI E ABHBeforeAfter(A)Any valueABHAs example, if we consider instruction MVI E, ABH then it means that ABH will be moved or copied to the register E. And, as a result, the previous value of E will get overwritten.AddressHex CodesMnemonicComment20001EMVI E, ABHE ← ABH2001ABABH as operandThis instruction will have seven T-states as shown below.Summary  − So this instruction MVI E, ABH requires 2-Bytes, 2-Machine ... Read More

Using 16-bit address, 8085 can access one of the 216= 64K locations. As a single hexadecimal digit can be expressed in4-bit notation so, in 8085, memory address can be expressed using four hexadecimal digits. Similarly, for convenience, we can represent all 8085 CPU registers as A, B, C etc. using binary notations. Internally 8085 specifies these registers using 0s and 1s only. So3-bits are just enough to represent a register. The 3-bit register codes for the registers of 8085 are shown in the following tableWith 3-bit register code, eight registers can be specified in maximum as 23= 8. On the ... Read More